1. Field of the Invention
This invention relates to semiconductor memory devices and more particularly to methods of manufacture of mask ROM memory devices and the devices produced thereby.
2. Description of Related Art
The manufacturing process turn around time for manufacture of conventional Mask ROM devices comprises on the order of several weeks. Poor yield prediction is always a problem that exists between the customer and the fabrication operators. On the other hand, the post-metal mask process can provide a short turn around time of a few days. However, the minimum dimension is limited by the ROM photolithographic resolution induced by the metal step height. The cell leakage is also a problem for the post metal ROM.
FIGS. 1A-1F show the process flow for producing a prior art conventional mask ROM device 20.
FIG. 1A shows a first phase of the process performed in manufacturing the device 20 which includes a P-- doped silicon substrate 21 with buried N+ bit lines 24. Over the substrate is formed a conventional blanket gate oxide layer 22 upon which is formed a polysilicon word line 23. Over the polysilicon word line 23 is a ROM code implant photoresist mask 25 with an array of openings 19 into which code implant boron B.sup.11 ions 26 are implanted in regions 27 between the buried N+ bit lines 24. After the code has been implanted, the prior art adds the code number process including a first step of forming a photoresist coating; second, exposing the number window; third, code etching; fourth, removing all photoresist.
As shown in FIG. 1B, above the polysilicon word line 23 is formed a blanket dielectric layer 28 of BPSG glass (BPSG (BoroPhosphoSilicate Glass)) which is a dielectric material that can be used as insulation between semiconductor device structures having a thickness of about 5,500.ANG. in which a contact hole opening 30 down to word line 23 has been formed by etching through a photoresist mask layer 29.
Then the photoresist mask layer 29 is removed.
Next, as shown in FIG. 1C, a blanket layer of titanium (Ti) 32 is sputtered onto device 20 covering the BPSG layer 28 and the exposed surface of word line 23. Next, the titanium is converted to titanium nitride (TIN) by the process of RTA (rapid thermal annealing.) The process is, first, heat to 600.degree. C. for 60 seconds and second heat to 780.degree. C. for 20-30 seconds with a source of NH.sub.3 +N.sub.2 extending down into contact with polysilicon layer 23 through opening 30 in dielectric layer 28.
Next, as shown in FIG. 1D, the device 20 is coated with a blanket layer of metal 34 (aluminum) with a thickness of 10k.ANG. formed at a temperature of 400.degree. C. by sputtering for 12 seconds, which extends into opening 30 in electrical contact with the polysilicon layer 23 through the titanium nitride (TIN) layer 32.
Referring to FIG. 1E, the blanket layer of metal 34 on device 20 has been patterned with photolithographic metallization mask with patterns 36 and 37 that were formed above layers 34 and 32 in FIG. 1D. Then an etching process is performed in which mask patterns 36 and 37 are used to protect metal structures 34', 34", 32', 32" which are formed by etching of metal layer 34 and TiN layer 32.
FIG. 1F shows the prior art device of FIG. 1E after the masks 36 and 37 have been removed.
After this stage of the process, the device is passivated in accordance with the state of the art.
FIGS. 5A-5C shows the process flow for producing another prior art conventional mask ROM device 20. FIG. 5A shows the first step performed upon a P-- doped silicon substrate 21 with buried N+ bit lines 24. Upon the substrate is a conventional blanket gate oxide layer 22 upon which is formed a blanket polysilicon layer 23 or word line 23.
As shown in FIG. 5B above the polysilicon layer 23 is formed a blanket dielectric layer 28 of BPSG glass having a thickness of about 3,000.ANG. in which a contact hole opening 30 has been formed into which a blanket layer of titanium (Ti) 32 is sputtered. Next, the titanium is converted to titanium nitride (TIN) by the process of RTA (rapid thermal annealing.) The process is, first, heat to 600.degree. C. for 60 seconds and second heat to 780.degree. C. for 20-30 seconds with a source of NH.sub.3 +N.sub.2 extending down into contact with polysilicon layer through opening 30 in dielectric layer 28.
Next, the device 20 was coated with a blanket layer of metal 34 (aluminum) with a thickness of 10k.ANG. formed at a temperature of 400.degree. C. by sputtering for 12 seconds, which extends into opening 30 in electrical contact with the polysilicon layer 23 through the titanium nitride (TIN) layer 32. The blanket layer of metal 34 on device 20 was patterned with metallization photolithographic mask with patterns 36 and 37. Mask patterns 36 and 37 are used to protect metal structures 34' and 34" and TiN structures 32' and 32" which are formed by etching of metal layer 34 and TiN layer 32.
Then a ROM code implant photoresist mask 65' is formed over structure 34' with a code ion implant of boron B.sup.11 ions 65 implanted in region 65" between a pair of buried N+ bit lines 24. After the code has been implanted and the prior art adds the code number process including code etching (in post-metal process, one can directly etch without another photoresist step because there is the BPSG layer as the buffer for the cell opening.)
FIG. 5C shows a perspective view of a TiN layer 32 above which is formed an aluminum layer 34.
In accordance with this invention, a method is provided for manufacturing a ROM semiconductor device on a semiconductor substrate. The method is performed on a substrate which includes an array of parallel buried bit lines integral buried therein oriented in a first direction. A gate oxide layer covers the substrate and word lines are formed above the gate oxide layer. A dielectric layer is formed over the word lines. A contact hole is formed in the dielectric layer. Then a blanket titanium nitride layer is formed over the device so that it extends into the contact hole. Then, over the device, form a ROM code mask having a ROM code opening therethrough, the opening being centered between a pair of the bit lines. Etch the titanium nitride layer through the ROM code opening, with the titanium nitride layer having a step height. Ion implant a code implant dopant through the ROM code opening down into a doped region in the substrate below the ROM code opening. Then remove the ROM code mask, followed by performing a rapid thermal annealing step. Then apply a blanket layer of metallization to the device including the contact hole, and pattern the metallization.
Preferably, the dielectric layer comprises a boron phosphorous glass material; and the dielectric has a thickness of within the range between about 2,000.ANG. and about 4,000.ANG..
Preferably, the dielectric has a thickness of about 3,000.ANG.; and the step height is within the range between about 400.ANG. and about 700.ANG.. More preferably, the step height is about 500.ANG..
Preferably, the rapid thermal annealing is performed within a range between about 650.degree. C. and about 850.degree. C.; and more preferably, the rapid thermal annealing is performed at about 750.degree. C.
In accordance with another aspect of the invention, a method is provided for manufacturing a ROM semiconductor device on a semiconductor substrate. At the outset of the method, the substrate includes an array of parallel buried bit lines integral therewith, the buried bit lines being oriented in a first direction, and a gate oxide layer above the substrate and word lines formed above the gate oxide layer.
The first step of the process comprises forming a dielectric layer over the word lines, followed by forming a contact hole in the dielectric layer. Then form a blanket titanium nitride layer over the device extending into the contact hole. Next, form a ROM code mask over the device, the ROM code mask having a ROM code opening and a code number opening therethrough, the ROM code opening being centered between a pair of the bit lines. Next, perform a TiN etching through the ROM code mask, followed by ion implanting a code implant dopant through the ROM code opening down into a doped region in the substrate below the ROM code opening. Then, remove the ROM code mask and the code number mask, and following that perform a rapid thermal annealing step. Next, apply a blanket layer of metal to the device including the contact hole, and pattern the metal.
Preferably, the dielectric layer comprises a material selected from BPSG and BPTEOS, and the dielectric has a thickness of within the range between about 2,000.ANG. and about 4,000.ANG. and preferably about 3,000.ANG..
Preferably, the step height is within the range between about 400.ANG. and about 700.ANG. and preferably about 500.ANG. and the rapid thermal annealing is performed within a range between about 650.degree. C. and about 850.degree. C., and preferably at about 750.degree. C.
Features and advantages of this invention are as follows:
(1) This invention provides a method of manufacturing a Mask ROM achieving a short turn around time of a few days as contrasted with the several week turn around time of conventional Mask ROM processes for a Chip on Board (COB) ROM product. PA1 (2) Manufacture of ROM products of the COB form requires the removal of a thin titanium nitride (TIN) film under a PAD window before metal sputtering to avoid a bonding problem between the metal and the TiN film. This invention provides a combined ROM mask and a PAD mask to remove the TiN layer on the cell circuit and in the PAD region, both at the same time. Both FIGS. 3 and 4A show cell structures. The PAD region is located on the periphery of the circuit for wire bonding. PA1 (3) When the TiN has been removed there are three advantages. First, the implant energy required is reduced. Second, the PAD region is removed in TiN for the COB device. Third, the oxide loss by TiN overetching can provide the code etching so another mask and etching cycle is not required. The ROM process can be implemented easily unlike the prior art post-metal process. PA1 (4) The additional RTA (Rapid Thermal Anneal Process) step following the ROM implantation in accordance with this invention is another advantage. This new RTA process fully activates the code implant region and reduces the high buried N+ (BN+) bit line sheet resistance resulting from code implant damage which results in lower resistance. PA1 (5) The advantage of full code activation is that it can provide a high code threshold voltage; and low implanted BN+ sheet resistance can reduce the current drop in the cell and reduce timing delay. The combination of both items achieves high circuit performance at high voltages. PA1 (6) The post-metal mask ROM process employs a low temperature furnace alloy (below 500.degree. C.) for code activation and implanted BN+ sheet resistance compensation. This low temperature process cannot make the circuit provide optimum performance, but a high temperature RTA step (750.degree. C.) in accordance with this invention does provide optimum performance. PA1 (7) Full activation in accordance with this invention can reduce the leakage current of a cell in comparison with post-metal ROM.
COB products use the aluminum wire bonding technology unlike the gold wire bonding technology using on conventional IC products. Aluminum wire bonding has higher stress between the aluminum and the TiN interface, so TiN must be removed for good adhesion.
In the prior art, there was a photolithographic limitation induced by the metal step height of typically 8k.ANG.-10k.ANG., whereas in accordance with this invention the step height has been reduced to about 500.ANG..
For example, in FIG. 5B, the post metal step height of layers 34' and 34" is about 8k.ANG.-10k.ANG.. In connection with this invention, the step height of layer 32" is about 500.ANG..